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Copy pathcadr4_olord2.vhd
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cadr4_olord2.vhd
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library ieee;
use ieee.std_logic_1164.all;
library ttl;
use ttl.sn74.all;
use ttl.other.all;
use ttl.unsorted.all;
library cadr4;
use cadr4.utilities.all;
entity cadr4_olord2 is
port (
\-ape\ : out std_logic;
\-mpe\ : out std_logic;
\-pdlpe\ : out std_logic;
\-dpe\ : out std_logic;
\-ipe\ : out std_logic;
\-spe\ : out std_logic;
\-higherr\ : out std_logic;
err : out std_logic;
\-mempe\ : out std_logic;
\-v0pe\ : out std_logic;
\-v1pe\ : out std_logic;
\-halted\ : out std_logic;
hi1 : out std_logic;
gnd : in std_logic;
aparok : in std_logic;
mmemparok : in std_logic;
pdlparok : in std_logic;
dparok : in std_logic;
clk5a : out std_logic;
iparok : in std_logic;
spcparok : in std_logic;
highok : out std_logic;
memparok : in std_logic;
v0parok : in std_logic;
vmoparok : in std_logic;
statstop : out std_logic;
\stat.ovf\ : in std_logic;
\-halt\ : in std_logic;
\-mclk5\ : out std_logic;
mclk5a : out std_logic;
\-clk5\ : out std_logic;
\-reset\ : out std_logic;
reset : out std_logic;
\bus.power.reset_l\ : out std_logic;
\power_reset_a\ : out std_logic;
\-upperhighok\ : in std_logic;
\-lowerhighok\ : out std_logic;
\-boot\ : out std_logic;
\prog.bus.reset\ : out std_logic;
\-bus.reset\ : out std_logic;
\-clock_reset_b\ : out std_logic;
\-clock_reset_a\ : out std_logic;
\-power_reset\ : out std_logic;
srun : in std_logic;
\boot.trap\ : out std_logic;
hi2 : out std_logic;
\-boot1\ : out std_logic;
\-boot2\ : out std_logic;
\-ldmode\ : out std_logic;
ldmode : out std_logic;
mclk5 : in std_logic;
clk5 : in std_logic;
\-busint.lm.reset\ : in std_logic;
\-prog.reset\ : out std_logic;
spy6 : in std_logic;
\-errhalt\ : out std_logic;
errstop : in std_logic;
\prog.boot\ : out std_logic;
spy7 : in std_logic);
end;
architecture ttl of cadr4_olord2 is
signal internal1 : std_logic;
signal internal2 : std_logic;
signal internal3 : std_logic;
signal internal4 : std_logic;
signal internal5 : std_logic;
signal nc75 : std_logic;
signal nc76 : std_logic;
signal nc77 : std_logic;
signal nc78 : std_logic;
signal nc79 : std_logic;
signal nc80 : std_logic;
signal nc81 : std_logic;
signal nc82 : std_logic;
signal nc83 : std_logic;
begin
olord2_1a02 : sn74s133 port map(g => \-ape\, f => \-mpe\, e => \-pdlpe\, d => \-dpe\, c => \-ipe\, b => \-spe\, a => \-higherr\, q_n => err, h => \-mempe\, i => \-v0pe\, j => \-v1pe\, k => \-halted\, l => hi1, m => hi1);
olord2_1a03 : sn74s374 port map(oenb_n => gnd, o0 => \-ape\, i0 => aparok, i1 => mmemparok, o1 => \-mpe\, o2 => \-pdlpe\, i2 => pdlparok, i3 => dparok, o3 => \-dpe\, clk => clk5a, o4 => \-ipe\, i4 => iparok, i5 => spcparok, o5 => \-spe\, o6 => \-higherr\, i6 => highok, i7 => memparok, o7 => \-mempe\);
olord2_1a05 : sn74s374 port map(oenb_n => gnd, o0 => \-v0pe\, i0 => v0parok, i1 => vmoparok, o1 => \-v1pe\, o2 => statstop, i2 => \stat.ovf\, i3 => \-halt\, o3 => \-halted\, clk => clk5a, o4 => nc76, i4 => nc77, i5 => nc78, o5 => nc79, o6 => nc80, i6 => nc81, i7 => nc82, o7 => nc83);
olord2_1a06 : sn74s37 port map(g1a => \-mclk5\, g1b => \-mclk5\, g1y => mclk5a, g2a => \-clk5\, g2b => \-clk5\, g2y => clk5a, g3y => \-reset\, g3a => hi1, g3b => reset, g4y => \bus.power.reset_l\, g4a => \power_reset_a\, g4b => \power_reset_a\);
olord2_1a07 : sn74s02 port map(g1q_n => highok, g1a => \-upperhighok\, g1b => \-lowerhighok\, g2q_n => \-boot\, g2a => internal5, g2b => internal2, g3b => \power_reset_a\, g3a => \prog.bus.reset\, g3q_n => \-bus.reset\, g4b => '0', g4a => '0');
olord2_1a11 : sn74s02 port map(g1q_n => \-clock_reset_b\, g1a => \power_reset_a\, g1b => internal1, g2q_n => \-clock_reset_a\, g2a => \power_reset_a\, g2b => internal1, g3b => gnd, g3a => \-power_reset\, g3q_n => \power_reset_a\, g4b => '0', g4a => '0');
olord2_1a18 : sn74ls109 port map(clr1_n => \-boot\, j1 => srun, k1_n => hi1, clk1 => mclk5a, pre1_n => \-clock_reset_a\, q1 => nc75, q1_n => \boot.trap\, clr2_n => '0', j2 => '0', k2_n => '0', clk2 => '0', pre2_n => '0');
olord2_1a19 : ic_16dummy port map(hi1 => hi1, hi2 => hi2, \-boot1\ => \-boot1\, \-boot2\ => \-boot2\, \-power_reset\ => \-power_reset\);
olord2_1a20 : sn74ls14 port map(g1q_n => internal4, g2a => \-boot1\, g2q_n => internal5, g3a => \-boot2\, g3q_n => internal3, g4q_n => \-power_reset\, g4a => internal4, g1a => '0', g5a => '0', g6a => '0');
olord2_1b10 : sn74s04 port map(g1a => \-ldmode\, g1q_n => ldmode, g3a => mclk5, g3q_n => \-mclk5\, g4q_n => \-clk5\, g4a => clk5, g6q_n => internal1, g6a => \-busint.lm.reset\, g2a => '0', g5a => '0');
olord2_1c07 : sn74s00 port map(g4q_n => \-lowerhighok\, g4a => hi2, g4b => hi1, g1b => '0', g1a => '0', g2b => '0', g2a => '0', g3b => '0', g3a => '0');
olord2_1c08 : sn74s10 port map(g3y_n => reset, g3a => \-boot\, g3b => \-clock_reset_b\, g3c => \-prog.reset\, g1a => '0', g1b => '0', g2a => '0', g2b => '0', g2c => '0', g1c => '0');
olord2_1c09 : sn74s00 port map(g2b => ldmode, g2a => spy6, g2q_n => \-prog.reset\, g4q_n => \-errhalt\, g4a => errstop, g4b => err, g1b => '0', g1a => '0', g3b => '0', g3a => '0');
olord2_1c18 : sn74s32 port map(g3y => internal2, g3a => internal3, g3b => \prog.boot\, g1a => '0', g1b => '0', g2a => '0', g2b => '0', g4a => '0', g4b => '0');
olord2_1d10 : sn74s08 port map(g2b => ldmode, g2a => spy7, g2q => \prog.boot\, g1b => '0', g1a => '0', g3a => '0', g3b => '0', g4a => '0', g4b => '0');
end architecture;