[wb_acq_core] reserved bits in use by HALCS aren't documented

[ericonr]

As seen in https://github.com/lnls-dig/halcs/blob/ae8a6a18c68cfed681517e12f7bf2d9a380d3c74/src/sm_io/modules/acq/sm_io_acq_exp.c#L39-L44

These bits are set as "reserved" in the '.wb' file, but are in fact used by the gateware to inform halcs about relevant conditions.

[augustofg]

Actually, there are even more reserved bits used by the wb_acq_core:

infra-cores/modules/wishbone/wb_acq_core/wb_acq_core.vhd

Lines 590 to 596 in a1b7144

	regs_in.sta_reserved1_i <= dbg_fifo_rd_empty & dbg_fifo_fc_rd_en & dbg_fifo_re & dbg_fifo_we;
	regs_in.sta_fc_trans_done_i <= fifo_fc_all_trans_done_l;
	regs_in.sta_fc_full_i <= fifo_sta_full;
	regs_in.sta_reserved2_i <= "00" & dbg_source_pl_stall & dbg_source_pl_dreq &
	dbg_fifo_fc_valid_fwft & dbg_fifo_wr_full;
	regs_in.sta_ddr3_trans_done_i <= ddr3_all_trans_done_l;
	regs_in.sta_reserved3_i <= f_gen_std_logic_vector(regs_in.sta_reserved3_i'length-

I'll update the wbgen file to include these.

[augustofg]

I couldn't guess exactly what all these reserved bits mean, but at least they are not marked as 'reserved' anymore here #16. We should check if everything works with halcs before merging.