Known Problems and Future Work

Here are a list of things that are currently not working, not up to date or not implemented

• Fir filter: The filter is not tested enough and the coefficients might not be optimal, This could be done a lot better and making it reliable would allow us to start using it in beamforming-lk. The optimal filter would be a band-pass with cutoff at 200Hz and 4 kHz but a high-pass with cutoff at 200Hz or low-pass with cutoff at 4 kHz would help.

• Simulated array: The simulated array was designed to run on the same FPGA as the sampler as well as on a separate FPGA connected together with jumper cables. Currently, the simulated array have to be fixed for both applications. The simulated array that runs on the same FPGA have the wrong timing since it had to be changed late when longer cables where introduced. Then the second problem is that the simulated array that runs on a separate FPGA have problems with the clocks making us miss some samples. This is a harder problem that might take a bit of work to fix.

• Simulated array order: This is just a small fix for the simulated array on the same FPGA as the sampler when we are running with four arrays that are not in the order of the connections (JE fisrt, JB second, JC third and JD last) it would be nice to also have the simulated array able to work in this order. This could simply be done by swapping some outputs in the simulated_array.vhd. It would be nice to have a parameter to set this from the top file 😄.

• Automatic delay calibration: There is currently an index created for each sample.vhd in the top file. This is a index for the delay length and it would be nice to have some sort of automatic setup of this number. This could be done by examining the most significant bit (MSB) and verifying that it matches the following 7 bits; if they do not match, the sample delay is not accurately calibrated. An automatic check for this that changes this index on the fly would be nice to reduce the amount of calibration needed.

• More automatic tests: Currently, we only have one automatic test for "tb_super_test.vhd", but it would be beneficial to build additional automatic tests for quick development and testing.

• Communication from PC to FPGA: It would be nice for the PC to be able to set some parameters on the FPGA, to reduce the need for rebuilding the VHDL code. This could be done by sending UDP packets from the PC to the FPGA (might be hard to implement) and then sending them down though AXI-Lite. This would allow the user to change the recording frequency, delays, debugging modes and more. This is probably a lot more work than the other points.

• Implement parts of or all of the beam-forming on the FPGA and the Zynq processor: This would be interesting to do but also a lot of work. If possible it would make a small and convenient package where both the sampling and beam-forming is done on the same development board. There might be a need for sending data back and forth from the FPGA and the ZYNQ to complete this feature but it should be possible 🚀. Remember to utilize the FPGA combined with both cores on the Zynq for maximum performance. 📈