stm32g0b1: proper PLL setup

candle-usb · Jan 16, 2023 · c6e229e · c6e229e
1 parent 926c013
commit c6e229e
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/include/config.h b/include/config.h
@@ -243,7 +243,7 @@ THE SOFTWARE.
 	#define DFU_INTERFACE_STRING_FS	 (uint8_t*) "budgetcan firmware upgrade interface"
 	#define CAN_INTERFACE			 FDCAN1
 	#define CAN_INTERFACE2			 FDCAN2
-	#define CAN_CLOCK_SPEED			 64000000
+	#define CAN_CLOCK_SPEED			 40000000
 	#define NUM_CAN_CHANNEL			 1
 //	#define CONFIG_CANFD
 
@@ -276,7 +276,7 @@ THE SOFTWARE.
 	#define DFU_INTERFACE_STRING_FS	 (uint8_t *)"NUCLEO-G0B1RE firmware upgrade interface"
 	#define CAN_INTERFACE			 FDCAN1
 	#define CAN_INTERFACE2			 FDCAN2
-	#define CAN_CLOCK_SPEED			 64000000
+	#define CAN_CLOCK_SPEED			 40000000
 	#define NUM_CAN_CHANNEL			 1
 //	#define CONFIG_CANFD
 

diff --git a/src/can/bxcanfd.c b/src/can/bxcanfd.c
@@ -34,7 +34,7 @@ void can_init(can_data_t *channel, FDCAN_GlobalTypeDef *instance)
 {
 	RCC_PeriphCLKInitTypeDef PeriphClkInit = {
 		.PeriphClockSelection = RCC_PERIPHCLK_FDCAN,
-		.FdcanClockSelection = RCC_FDCANCLKSOURCE_PCLK1,
+		.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL,
 	};
 
 	HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

diff --git a/src/device/device_g0.c b/src/device/device_g0.c
@@ -49,10 +49,10 @@ void device_sysclock_config(void) {
 	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 	RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
-	RCC_OscInitStruct.PLL.PLLN = 8;
+	RCC_OscInitStruct.PLL.PLLN = 20;
 	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-	RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
-	RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+	RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV8;
+	RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV5;
 	HAL_RCC_OscConfig(&RCC_OscInitStruct);
 	/** Initializes the CPU, AHB and APB buses clocks
 	*/