modules/wb_acq_core: fix last word detection in transaction

For AXIS, we must assert the PLD_LAST signal on the
last word for a transaction before issuing a new command
on the CMD interface. The condition to detect the last
word has 2 possibilities:

1) Specified number of words written to the DDR3 controller,
typical case in "immediate"" acquisition, and this worked fine.

2) DDR3 AXIS address going over the limit and wrapping back
to the start address. This was always asserting the last word
detection (ddr_eop signal) on the first word of the next
transaction, causing the last word to be written past
the DDR3 end address and the next word to be written
correctly at the DDR start address.

The fix for the case #2 was a simple "=", as we need to consider
the case for the DDR end address to be aligned with the
"ddr_addr_cnt_axis + c_addr_ddr_inc_axis", which is the
condition to the counter to be the last one on the next word.

This was reported by Scott Cogan, from FRIB. Thanks Scott.

modules/wishbone/wb_acq_core/acq_ddr3_axis_write.vhd

@@ -675,8 +675,8 @@ begin
   ddr_btt <= ddr_btt_full(ddr_btt'left downto 0);
 
   -- calculate if the next address will go over the limit
-  ddr_addr_cnt_next_will_reach_max <= '1' when ddr_addr_cnt_axis + c_addr_ddr_inc_axis > ddr_addr_max else '0';
-  ddr_addr_cnt_m1_next_will_reach_max <= '1' when ddr_addr_cnt_axis + c_addr_ddr_inc_axis > ddr_addr_max_m1 else '0';
+  ddr_addr_cnt_next_will_reach_max <= '1' when ddr_addr_cnt_axis + c_addr_ddr_inc_axis >= ddr_addr_max else '0';
+  ddr_addr_cnt_m1_next_will_reach_max <= '1' when ddr_addr_cnt_axis + c_addr_ddr_inc_axis >= ddr_addr_max_m1 else '0';
   -- We must compare the limit using >=, as the input wr_end_addr_alig may not
   -- be multiple of "c_addr_ddr_inc_axis". Thus not allowing us to use "=" only
   ddr_addr_cnt_max_reached <= '1' when ddr_addr_cnt_axis >= ddr_addr_max else '0';