axi3

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5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

arm pipeline cache processor verilog systemverilog computer-architecture testbench verilog-hdl risc-v digitaldesign axi3

Xillinx AXI Verification IP VLNV:axi_vip1.1@Vivado 2017.4

bfm axi3

Xillinx AXI Verification IP :axi_vip1.1@Vivado 2017.4

vip bfm xillinx axi3

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