This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.
layout cadence-virtuoso cadence nmos vlsi-circuits vlsi-design pmos cmos-circuits cmos-vlsi cmos-logic low-power-vlsi-design
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Updated
Jan 6, 2025