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FIRRTL/Chisel version bumps + reduction unary operators #4

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FIRRTL/Chisel version bumps + reduction unary operators #4

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b37c78f
Bump chisel/firrtl
noloerino Mar 15, 2021
95d7d55
Implement translation for cvt/andr/orr/xorr unary ops
noloerino Mar 16, 2021
d9a344c
Fix bv index in unops
noloerino Mar 16, 2021
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4 changes: 2 additions & 2 deletions build.sbt
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,9 @@ resolvers ++= Seq(

// Managed dependency on latest FIRRTL + chisel3
//libraryDependencies += "edu.berkeley.cs" %% "firrtl" % "1.2.0-RC1"
libraryDependencies += "edu.berkeley.cs" %% "firrtl" % "1.3.2"
libraryDependencies += "edu.berkeley.cs" %% "firrtl" % "1.4.2"
//libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.2.0-RC1"
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.3.2"
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.2"

libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.9"

21 changes: 20 additions & 1 deletion src/main/scala/chiselucl/backend/UclidEmitter.scala
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Expand Up @@ -94,11 +94,30 @@ class UclidEmitter extends Transform with DependencyAPIMigration {

private def serialize_unop(p: DoPrim, arg0: String): String = p.op match {
case Neg => s"-$arg0"
case Not => s"~${arg0}"
case Not => s"~$arg0"
// TODO: Handle asUInt operator
case AsUInt => arg0
// TODO: Handle asSInt operator
case AsSInt => arg0
case Cvt =>
// Converts unsigned to signed
val dstLen = get_width(p.tpe)
val srcLen = get_width(p.args.head.tpe)
val diff = dstLen - srcLen
if (diff == 0) {
arg0
} else {
s"bv_sign_extend($diff, $arg0)"
}
case Andr | Orr | Xorr =>
// Simulate bitwise reduction operators
(0 until get_width(p.args.head.tpe)).map(i => s"$arg0[$i:$i]").mkString(
p.op match {
case Andr => " & "
case Orr => " | "
case Xorr => " ^ "
}
)
case _ => throwInternalError(s"Illegal unary operator: ${p.op}")
}

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